The present invention relates generally to a semiconductor device having a Multi Chip Module (MCM) structure and a method of manufacturing such semiconductor device. More particularly, the present invention relates to a semiconductor device and a method of manufacturing such semiconductor device in which a plurality of semiconductor chips are stacked and in which a larger semiconductor chip can be appropriately stacked over a smaller semiconductor chip.
Recently, in order to avoid an expansion of mounting area or areas of semiconductor devices and to increase mounting density, there are proposed various types of semiconductor devices having a stacked MCM structure. For example, there is proposed a semiconductor device having a stacked Chip Size Package (CSP) structure in which a plurality of semiconductor chips are closely stacked and mounted on a wiring board or substrate.
FIG. 3 is a cross sectional view showing a conventional semiconductor device having such stacked CSP structure (prior art 1). In the semiconductor device shown in FIG. 3, a lower side semiconductor chip 102 is bonded onto a surface of a wiring substrate 101 via insulating adhesive and the like, and an upper side semiconductor chip 103 is stacked and bonded onto the lower side semiconductor chip 102 via insulating adhesive and the like. On the surface of the wiring substrate 101, there is formed a wiring layer having wiring patterns (not shown in the drawing) On the top surfaces of the lower side semiconductor chip 102 and of the upper side semiconductor chip 103, there are formed electrodes, i.e., bonding pads, 102a and 103a, respectively. These electrodes 102a and 103a are coupled with electrodes 101a formed on the wiring substrate 101 via bonding wires 104 and 105 made of gold and the like, respectively, and thereby the lower side semiconductor chip 102 and the upper side semiconductor chip 103 are electrically coupled with the wiring patterns on the wiring substrate 101.
Also, there are disposed a plurality of solder balls 106 on the backside surface of the wiring substrate 101. The solder balls 106 are coupled with the wiring patterns formed on the surface of the wiring substrate 101 via holes provided in the wiring substrate 101 (not shown in the drawing). Thereby, the lower side semiconductor chip 102 and the upper side semiconductor chip 103 are electrically coupled with the solder balls 106. Further, on the wiring substrate 101, there is formed an encapsulation resin 107 for encapsulating the lower side semiconductor chip 102, the upper side semiconductor chip 103 and the bonding wires 104 and 105.
In the semiconductor device mentioned above, the upper side semiconductor chip 103 disposed on the upside is, for example, a memory IC chip, such as a DRAM device and the like. The lower side semiconductor chip 102 disposed on the downside is, for example, a system IC chip, such as a microprocessor and the like. The size of the upper side semiconductor chip 103 is made smaller than that of the lower side semiconductor chip 102 such that the electrodes of the lower side semiconductor chip 102 on the downside can be exposed.
However, according to an advance in semiconductor technology, the feature size of a semiconductor integrated circuit prescribed by the design rule becomes smaller and smaller. Therefore, the size of a semiconductor chip becomes smaller as the feature size becomes smaller while retaining the same function. Thus, according to the reduction of the feature size, there is a possibility that the size of the lower side semiconductor chip 102 becomes smaller than that of the upper side semiconductor chip 103. In such case, conventionally, the lower side semiconductor chip 102 having a smaller size and the upper side semiconductor chip 103 having a larger size are replaced upside down. That is, the upper side semiconductor chip 103 is mounted on a wiring substrate and the lower side semiconductor chip 102 is mounted on the upper side semiconductor chip 103. Therefore, conventionally, the semiconductor chip having a smaller size is always used as the upper side semiconductor chip and the semiconductor chip having a larger size is always used as the lower side semiconductor chip, so that when both the semiconductor chips are stacked on a wiring substrate, electrodes, i.e., bonding pads, of the semiconductor chip on the lower side are not hidden by the semiconductor chip on the upper side. Thus, it is possible to couple electrodes of the semiconductor chips on both the upper side and lower side with wiring patterns on the wiring substrate via metal wires.
Japanese patent laid-open publication No. 2000-269408 discloses another type of semiconductor device having a stacked MCM structure, which is hereafter referred to as prior art 2. In the semiconductor device of the prior art 2, interference between semiconductor chips caused by stacking or bonding the semiconductor chips directly are avoided and degree of freedom of wiring of the wiring substrate can be improved.
FIG. 4 is a cross sectional view showing the semiconductor device of the prior art 2. In the semiconductor device shown in FIG. 4, on the upper surface of a multi-layer wiring substrate 201, a lower side semiconductor chip 202 is bonded by using adhesive and the like. Electrodes (not shown in the drawing) formed on the upper surface of the multi-layer wiring substrate 201 are coupled with electrodes (not shown in the drawing) formed on the upper surface of the lower side semiconductor chip 202 via bonding wires 203. On the upper surface of the lower side semiconductor chip 202, various circuit elements are also formed. Solder balls 204 are disposed on the under side surface of the multi-layer wiring substrate 201, and are coupled with multi-layer wiring conductors formed on the upper side surface of the multi-layer wiring substrate 201 via holes formed in the substrate 201.
Also, on the multi-layer wiring substrate 201, spacers or dam members 205 are formed which have a height larger than the thickness of the lower side semiconductor chip 202. On the dam member 205, lead portions 206b of a lead frame 206 are disposed. An upper side semiconductor chip 207 is bonded on a stage portion 206a of the lead frame 206. Also, electrodes (not shown in the drawing) formed on the upper surface, i.e., the surface on which circuits are formed, of the upper side semiconductor chip 207 are connected to the lead portions 206b via bonding wires 208. Further, the lead portions 206b and the multi-layer wiring of the substrate 201 are coupled via bonding wires 209. By this structure, the upper side semiconductor chip 207 is held at a location which is over the lower side semiconductor chip 202 and which is separated from the lower side semiconductor chip 202, and also the upper side semiconductor chip 207 is electrically coupled with the multi-layer wiring substrate 201. Further, these upper side semiconductor chip 207 and lower side semiconductor chip 202, the space between these chips 207 and 202, the dam members 205 and the bonding wires 203, 208 and 209 are encapsulated by an encapsulation resin 210.
However, in the semiconductor device of the above-mentioned prior art 1, when the design rule has changed, it becomes necessary to replace the semiconductor chips upside down. In such case, it is necessary to redesign the wiring substrate and fabricate it again. Therefore, manufacturing costs of the semiconductor device of the prior art 1 become high.
In the semiconductor device of the above-mentioned prior art 2, it is necessary to couple the lead portions 206b on the dam member 205 with the multi-layer wiring substrate 201 via bonding wires 209. Therefore, bonding times become large, and wiring structure becomes complicated. Also, the lead frame 206 for mounting the upper side semiconductor chip 207 is required. Therefore, manufacturing costs of the semiconductor device the prior art 2 also become high.
Therefore, it is an object of the present invention to provide a semiconductor device having a stacked Multi Chip Module structure in which a larger semiconductor chip can be appropriately stacked over a smaller semiconductor chip, and to provide a method of manufacturing such semiconductor device.
It is another object of the present invention to provide a semiconductor device having a stacked Multi Chip Module structure in which a larger semiconductor chip can be appropriately stacked over a smaller semiconductor chip and which has a simple structure, and to provide a method of manufacturing such semiconductor device.
It is still another object of the present invention to provide a stacked MCM type semiconductor device which can be manufactured at low cost even if the chip size or sizes of the semiconductor device have changed due to the change of the design rule, and to provide a method of manufacturing such semiconductor device.
It is still another object of the present invention to obviate the disadvantages of conventional semiconductor devices having a stacked Multi Chip Module structure.
According to an aspect of the present invention, there is provided a semiconductor device comprising: a wiring substrate; a lower side semiconductor chip bonded onto a surface of the wiring substrate; an upper side semiconductor chip; one or more spacers which are bonded onto the surface of the wiring substrate and which support the upper side semiconductor chip over the lower side semiconductor chip and at a location separated from the lower side semiconductor chip; conductors which electrically couple the upper side semiconductor chip and the lower side semiconductor chip with the wiring substrate; and an encapsulating resin portion which encapsulates the upper side semiconductor chip, the lower side semiconductor chip, the one or more spacers and the conductors on the wiring substrate.
In this case, it is preferable that the size of the upper side semiconductor chip is larger than that of the lower side semiconductor chip.
It is also preferable that lower end portion or portions and upper end portion or portions of the one or more spacers are bonded to the wiring substrate and the upper side semiconductor chip, respectively, via insulating adhesive.
It is further preferable that the wiring substrate and the one or more spacers are bonded via the conductors interposed therebetween and by using insulating adhesive.
It is advantageous that the one or more spacers comprise a single spacer member.
It is also advantageous that the one or more spacers comprise a plurality of spacer members.
It is further advantageous that the semiconductor device further comprises solder bumps disposed on the backside of the wiring substrate.
It is preferable that the lower side semiconductor chip is a system IC chip and the upper side semiconductor chip is a memory IC chip.
It is also preferable that the conductors are bonding wires made of gold or gold alloy.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: preparing a wiring substrate; mounting a lower side semiconductor chip onto a surface of the wiring substrate; electrically coupling the lower side semiconductor chip with the wiring substrate via conductors; bonding one or more spacers onto the surface of the wiring substrate by using insulating adhesive; bonding an upper side semiconductor chip onto the one or more spacers by using insulating adhesive to support the upper side semiconductor chip over the lower side semiconductor chip and at a location separated from the lower side semiconductor chip; electrically coupling the upper side semiconductor chip with the wiring substrate via conductors; and encapsulating the upper side semiconductor chip, the lower side semiconductor chip, the one or more spacers and the conductors on the wiring substrate 1 with encapsulating resin.
In this case, it is preferable that, in the bonding one or more spacers onto the surface of the wiring substrate by using insulating adhesive, the one or more spacers are bonded onto the wiring substrate via the conductors interposed therebetween.
It is also preferable that the size of the upper side semiconductor chip is larger than that of the lower side semiconductor chip.
It is further preferable that the one or more spacers comprise a single spacer member.
It is advantageous that the one or more spacers comprise a plurality of spacer members.
It is also advantageous that the method further comprises disposing solder bumps on the backside of the wiring substrate.
In the above-mentioned semiconductor device, when a plurality of semiconductor chips are stacked on a wiring substrate, a semiconductor chip disposed upside is supported over a semiconductor chip disposed below by using spacer or spacers. Therefore, even when the size of the semiconductor chip disposed below becomes smaller than that of the semiconductor chip disposed upside, it is possible to easily realize electrical connection between the semiconductor chip disposed below and the wiring substrate.
By using insulating adhesive to bond the spacer or spacers with the wiring substrate, it is possible to bond the spacer or spacers with the wiring substrate via the conductive wires which are interposed therebetween and which electrically couple the semiconductor chip disposed downside and the wiring substrate. Therefore, it is not necessary to previously reserve area or areas on the wiring substrate for bonding the spacers.